Data strobe multiplexer

ABSTRACT

Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.16/022,307, filed Jun. 28, 2018, which is incorporated herein byreference in its entirety.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory including volatile and non-volatilememory. Volatile memory can require power to maintain data and includesrandom-access memory (RAM), dynamic random-access memory (DRAM), andsynchronous dynamic random-access memory (SDRAM), among others.Non-volatile memory can provide persistent data by retaining stored datawhen not powered and can include NAND flash memory, NOR flash memory,read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM),Erasable Programmable ROM (EPROM), and resistance variable memory suchas phase change random access memory (PCRAM), resistive random-accessmemory (RRAM), and magnetoresistive random access memory (MRAM), 3DXPoint™ memory, among others.

Memory cells are typically arranged in a matrix or an array. Multiplematrices or arrays can be combined into a memory device, and multipledevices can be combined to form a storage volume of a memory system,such as a solid-state drive (SSD), a Universal Flash Storage (UFS™)device, a MultiMediaCard (MMC) solid-state storage device, an embeddedMMC device (eMMC™), etc.

A memory system can include one or more processors or other memorycontrollers performing logic functions to operate the memory devices orinterface with external systems. The memory matrices or arrays caninclude a number of blocks of memory cells organized into a number ofphysical pages. The memory system can receive commands from a host inassociation with memory operations, such as read or write operations totransfer data (e.g., user data and associated integrity data, such aserror data and address data, etc.) between the memory devices and thehost, erase operations to erase data from the memory devices, or performone or more other memory operations.

Memory is utilized as volatile and non-volatile data storage for a widerange of electronic applications, including, for example, personalcomputers, portable memory sticks, digital cameras, cellular telephones,portable music players such as MP3 players, movie players, and otherelectronic devices. Memory cells can be arranged into arrays, with thearrays being used in memory devices.

Many electronic devices include several main components: a hostprocessor (e.g., a central processing unit (CPU) or other mainprocessor); main memory (e.g., one or more volatile or non-volatilememory device, such as dynamic RAM (DRAM), mobile or low-powerdouble-data-rate synchronous DRAM (DDR SDRAM), etc.); and a storagedevice (e.g., non-volatile memory (NVM) device, such as flash memory,read-only memory (ROM), an SSD, an MMC, or other memory card structureor assembly, or combination of volatile and non-volatile memory, etc.).In certain examples, electronic devices can include a user interface(e.g., a display, touch-screen, keyboard, one or more buttons, etc.), agraphics processing unit (GPU), a power management circuit, a basebandprocessor or one or more transceiver circuits, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsmay describe similar components in different views. Like numerals havingdifferent letter suffixes may represent different instances of similarcomponents. The drawings illustrate generally, by way of example, butnot by way of limitation, various embodiments discussed in the presentdocument.

FIGS. 1-5 illustrate example embedded MultiMediaCard (eMMC™) systems, orportions of eMMC systems, including a host device, an eMMC device, and acommunication interface.

FIGS. 6-8 illustrate example timing diagrams of signals in an eMMCsystem.

FIG. 9 illustrates an example portion of an eMMC system.

FIG. 10 illustrates a block diagram of an example machine upon which anyone or more of the techniques (e.g., methodologies) discussed herein mayperform.

DETAILED DESCRIPTION

The Joint Electron Device Engineering Council (JEDEC) has promulgatednumerous interface and communication standards for embeddedMultiMediaCard (eMMC™) devices, including the JEDEC standard D84-B51(JESD84-A51), commonly referred to as JEDEC eMMC standard 5.1.

The present inventors have recognized, among other things, that a hostdevice can determine a timing relationship between a data strobe signaland an internal clock signal to align read data for sampling. In otherexamples, a data strobe pin can be used to provide data to the hostdevice, or a multiplexer circuit can be configured to provide a datastrobe signal to the host device in a calibration mode and a data signalto the host device in a data read mode.

FIG. 1 illustrates an example eMMC system 100 including a host 105 andan eMMC 110. The host 105 can include a host processor, a centralprocessing unit, or one or more other processor or controller, such asin an electronic (or host) device. The host 105 and the eMMC 110 cancommunicate using a communication interface including one or morebidirectional command and data lines (e.g., a command line (CMD) 111,data lines (DAT[7:0]) 113, etc.), such as defined in one or more JEDECstandards. To synchronize communication of data between the eMMC 110 andthe host 105, such as over the eight parallel data lines 113 illustratedin FIG. 1, the host 105 can provide a clock signal to the eMMC 110, forexample, using a clock line (CLK) 112. In other examples, thecommunication interface one or more other lines (not shown), such asreset, power/voltage levels (e.g., VCC, VSS, etc.), etc.

Each of the host 105 and the eMMC 110 can include a number of receiveror driver circuits configured to send or receive signals over thecommunication interface (e.g., command, data, or one or more otherlines, such as CMD, DAT[7:0], CLK, etc.), or interface circuits, such asdata control units, sampling circuits, or other intermedia circuitsconfigured to process data to be communicated over, or otherwise processdata received from the communication interface for use by the host 105,the eMMC 110, or one or more other circuits or devices.

The eMMC 110 can include a memory array (e.g., one or more arrays ofmemory cells, such as a NAND flash memory array, or one or more othermemory arrays) and a memory controller. The memory controller caninclude an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), or one or more other processing circuitsarranged or programmed to manage data transfers or operations to, from,or within the memory array.

In a read operation, the eMMC 110 can provide data (e.g., read data)from the memory array to the data lines 113 according to the clocksignal on the clock line 112 from the host 105 (e.g., at rising edges ofthe clock signal, falling edges of the clock signal, or both rising andfalling edges of the clock signal). However, as the data lines 113 areimperfect conductors having resistance, inductance, and capacitance,transitions on the data lines 113 from high to low, or low to high, whenthey occur (the value of a data line may remain constant for multipleclock transitions), take time. Further, as the working frequency of theeMMC 110 increases, the clock period decreases (in certain examples,approaching the propagation delay), and thus, the time period forsampling the data lines 113 becomes smaller. Accordingly, as thesampling time decreases, synchronizing communication between the host105 and the eMMC 110, such as to avoid sampling during transitions, canbecome challenging. To improve synchronization, the JEDEC eMMC standard5.0 introduced a data strobe signal from the eMMC 110 to the host 105.

During high-speed modes (e.g., HS400, with double data rate (DDR)transfer of data at both rising and falling edges of a 200 MHz clocksignal (400 MB/s), etc.), the eMMC 110 can provide a data strobe signalon a data strobe line (DS) 114 to the host 105, the data strobe signalsynchronous to data transitions on the data lines 113, such as to assistwith sampling (e.g., use as a clock signal at the host 105, etc.).However, this presents several issues. For example, the data strobesignal is only provided in a high-speed mode (e.g., HS400), and is thusnot present for all operations requiring sampling at the host 105. Onesolution is to multiplex the data strobe signal and the internal clocksignal at the host 105. However, in certain technologies (e.g., FPGA),it can be challenging to switch the multiplexer circuit fast enough tonot lose data or introduce errors at sampling (e.g., losing samplingedges, etc.). Moreover, the data strobe disappears at the end of thehigh-speed data read, when the internal data path within the host 105must continue to operate. Accordingly, there may not be enough datastrobe clock cycles to implement synchronization of the internal clockand the data strobe signal. In other technologies (e.g., ASIC),synchronizing data transitions from a data strobe to the clock can stillbe an issue. Moreover, using the data strobe as a clock signal requiressubstantial architecture changes, in certain examples requiring asubstantial amount of effort, including high development and time costs.

The present inventors have recognized, among other things, that the host105 can determine a timing relationship between the data strobe signaland an internal clock signal (e.g., the clock signal from the clock line112), such as to align read data on the data lines 113 for sampling, forexample, using one or more delay circuits. The host 105 can use the datastrobe signal to determine the transition time of the data on the datalines 113, and accordingly, the propagation delay between the eMMC 110and the host 105. The host 105 can use the transition time, or thepropagation delay, to determine a sampling time (e.g., the data strobetransition time plus a delay, such as a portion of the clock period,etc.), such as to avoid sampling during data strobe transitions, andaccordingly, data line transitions.

FIG. 2 illustrates an example portion of an eMMC system 200 including ahost 205, an eMMC 210, and a communication interface including a clockline (CLK) 212, data lines (DAT[7:0]) 213, and a data strobe line (DS)214. The host 205 can include a clock generator circuit (CKGEN) 220configured to provide a clock signal to the eMMC 210 using the clockline 212. The communication interface can include one or more additionallines, not shown, such as a command line (CMD), a reset line (RESET),etc.

The eMMC 210 can include a memory array and a memory controller, and canprovide data from the memory array to the host 205, or receive data fromthe host 205 to be stored on the memory array, using the data lines 213according to the clock signal on the clock line 212. The eMMC 210 cansample data received on the data lines 213 according to the data strobesignal, or provide data to the data lines 213 according to the clocksignal. Although the host 205 provides the clock signal, the propagationdelay between the host 205 and the eMMC 210 can be unknown, and incertain examples, can change under various conditions (e.g., temperaturechanges, supply voltage levels, etc.), including within or during longread operations. Accordingly, the eMMC 210 can provide a data strobesignal corresponding to data transitions (where applicable) on the datalines 213. The data strobe signal can be related to the clock signalfrom the host 205, the propagation delay of the communication interfacebetween the host 205 and the eMMC 210, and any processing delay withinthe eMMC 210 (e.g., between the memory controller and the memory array,etc.).

The host 205 can include a first sampling stage circuit (FSS) 215configured to sample data on the data lines 213. The FSS circuit 215 canbe configured to apply a delay to the data strobe signal, or to receivea delayed data strobe signal from a first delay circuit 225 (e.g., aprogrammable, selectable, adjustable, or other analog or digital delaycircuit, such as an FPGA delay component configured to provide aconfigurable delay). In certain examples, the delay circuits referred toherein can be a component of the host 205, or in other examples, can bean external component separate from but between the host 205 and theeMMC 210, but controlled by general-purpose input/output (IO) of thehost 205.

However, even as the JEDEC eMMC standards now provide for a data strobesignal for high-speed modes, the data strobe signal is not required inlow-speed modes (e.g., HS, HS200 (200 MB/s at 200 MHz, etc.), or anymode of communication or data transfer slower than a high-speed mode(e.g., HS400, etc.). In certain examples, the data strobe signal is notprovided in low-speed modes. If an eMMC is not in high-speed mode (e.g.,HS400, etc.), the data lines must be sampled using the clock signal.Accordingly, eMMC systems continue to support previous methods ofsampling data lines. Further, certain vendors, systems (e.g., hosts,eMMC devices, etc.), or other hardware or software remain incompatiblewith the data strobe feature. Certain vendors refuse to add another pinon the host or the eMMC device, or another line on the communicationinterface, or refuse to update or modify existing features, hardware, orsoftware to support the feature. Even in systems that support the datastrobe feature, if such feature is used only during high-speed modes,use may be intermittent, such that calibration remains an issue.

In other examples, low and high-speed modes can refer to lower that donot require a data strobe signal or calibration, and separately, higherspeeds higher than the lower speeds that do require a data strobe signalor calibration for effective communication, e.g., without data samplingerrors. In other examples, low and high-speed modes can refer to SDRsampling and DDR sampling, respectively.

Certain eMMC systems or components (e.g., hosts, eMMC devices, memorycontrollers, memory arrays, etc.) are capable of operating in high-speedmodes (e.g., HS400, etc.), but do not support the data strobe feature,for example, in hardware or software. The present inventors haverecognized, among other things, that certain eMMC systems or componentswithout the data strobe feature (e.g., the data strobe signal, datastrobe line, or software controlling such feature, etc.) can becalibrated for high-speed communication. In other examples, the datastrobe line 214 (e.g., after calibration) can be reallocated as anadditional data line (e.g., DAT[8], etc.).

FIG. 3 illustrates an example portion of an eMMC system 300 including ahost 305, an eMMC 310, and a communication interface including a clockline (CLK) 312 and data lines (DAT[7:0]) 313. The host 305 can include afirst sampling stage circuit (FSS) 315 or other sampling circuitconfigured to sample data on the data lines 313, and a clock generatorcircuit (CKGEN) 320 configured to provide a clock signal to the eMMC 310using the clock line 312.

In the absence of a data strobe signal or a data strobe line (or incertain examples, in combination therewith), the host 305 can includeone or both of a data delay circuit 316 configured to delay the datafrom the data lines 313, or a clock delay circuit 321 configured todelay the clock signal from the clock generator circuit 320, such thatthe first sampling stage circuit 315 is configured to sample the datalines 313 outside of the transition periods of the data signals,accounting for propagation or other delay between the host 305 and theeMMC 310 or within the host 305 or the eMMC 310. In certain examples,one or both of the data delay circuit 316 or the clock delay circuit 321can be determined using detected error rates (e.g., of known sampledata, for example, including transitions at every clock cycle, or aknown transition pattern, etc.), sampling at different delay values todetermine transition periods, or one or more other method to determinetransitions on the data lines 313. The delay of the delay circuits(e.g., the data delay circuit 316 or the clock delay circuit 321) can beconfigurable, the values selected by comparing results over one or moreread operations.

However, whereas certain data modes, such as HS200, provide a dedicateddata block having a known pattern for tuning communication variables,such as delay circuits, propagation delay, etc., the HS400 mode does notprovide such dedicated data block. Further, during long read operationsor other use conditions, operating conditions may change (e.g.,temperature, supply voltage, etc.), such that the location of a validdata window may change with respect to the sampling clock of the host305. When in use, a data strobe signal tracks changes in operatingconditions. However, when intermittently using the data strobe signal tocalibrate the propagation delay, the calibration can either be regularlychecked (e.g., at predetermined intervals, a specific time period,number of clock cycles, read operations, etc.), checked in response todetected errors (e.g., a threshold number of detected errors, errorrates above a threshold, etc.), or a change in conditions (e.g.,temperature change, supply voltage change, etc.). In betweencalibration, the data strobe line (such as illustrated in FIGS. 1 and 2)can be used to transfer data between the eMMC 310 and the host 305(e.g., from the eMMC 310 to the host 305 in response to a read command,etc.).

In other examples, one or more of the host 305, the eMMC 310, or thecommunication interface can include a data strobe line, a data strobepin, or a data strobe signal. However, in certain examples, one or morecomponent of the eMMC system 300 may not support the data strobe signal.In such conditions, the data strobe line can be used to transfer datafrom the eMMC 310 to the host 305, while calibrating the propagationdelay between the eMMC 310 and the host 305, and thus, the delay of oneor more delay circuits, using one or more other methods, such assampling at different delay values, or comparing results over one ormore read operations, etc.

FIG. 4 illustrates an example portion of an eMMC system 400 including ahost 405, an eMMC 410, and a communication interface including a clockline (CLK) 412, data lines (DAT[7:0]) 413, and a data strobe line (DS)414. The host 405 can include a first sampling stage circuit (FSS) 415or other sampling circuit configured to sample data on the data lines413, a clock generator circuit (CKGEN) 420 configured to provide a clocksignal to the eMMC 410 using the clock line 412, and a measurementcircuit (MEAS) 425, implemented in hardware, software, or a combinationof hardware or software.

In an example, the measurement circuit 425 can be configured to evaluatethe value of a delay to apply to a delay circuit, such as a data delaycircuit 416 configured to delay the data on the data lines 414 beforereaching the first sampling stage circuit 415. The measurement circuit425 can receive the clock signal from the clock generator circuit 420,and a data strobe signal from the eMMC 410, and can determine apropagation delay between the clock signal at the host 405 and the datastrobe signal received from the eMMC 410. The measurement circuit 425can determine the delay as a function of the alignment of transitions onthe clock signal and the data strobe signal, or can be configured toselect one of a plurality of predetermined delays, such as using a bestfit analysis, or a closest fit between the propagation delay and one ormore predetermined delay values. In an example, a result of themeasurement circuit 425 can be evaluated, such as by a host processor orone or more other component of the host 405, either in software orhardware. The data delay circuit 416 can be a component of the firstsampling stage circuit 415, or a separate component, as illustrated inFIG. 4, and can be controlled by the measurement circuit 425 or one ormore other component of the host 405.

In HS400 mode, the data strobe signal represents a dual data rate (DDR)pattern of data, continuously switching (1-0-1-0- . . . ) at each clockedge, rising and falling, representing a critical pattern to test thesampling capability of the host 405. The data strobe signal pattern isindependent to data on an accessed block of the eMMC 410. In certainexamples, the first sampling stage circuit 415 can remain unchanged, anda data delay circuit 416 can be applied to the data lines 413, but thevalue of the delay can be measured using the data strobe signal. Themeasurement circuit 425 can evaluate the data strobe signal on the datastrobe line 414, use the data strobe signal to determine the delay forthe data delay circuit 416 (e.g., alignment of the data strobe signal tothe clock signal, etc.). Then, after the delay is determined, a datastrobe delay circuit 426 can apply a delay to the data strobe line 413(e.g., equal to the delay of the data delay circuit 416). The datastrobe line 413, when not in use for calibration of the propagationdelay between the host 405 and the eMMC 410, can be used as anadditional data line (e.g., DAT8) between the eMMC 410 and the host 405,such as for read, write, or one or more other memory or data transferoperations. When intermittently using the data strobe signal tocalibrate the propagation delay, the calibration can either be regularlychecked (e.g., at predetermined intervals, a specific time period,number of clock cycles, read operations, etc.), checked in response todetected errors (e.g., a threshold number of detected errors, errorrates above a threshold, etc.), or a change in conditions (e.g.,temperature change, supply voltage change, etc.). In certain examples,the delay of one or more of the delay circuits can be evaluated,determined, or executed by hardware, software, or a combination thereof.

In other examples, in a system not having the data strobe feature, oneof the data lines 413 can provide a data strobe signal to the host 405for calibration purposes, for example, providing a pattern of data,continuously switching (1-0-1-0- . . . ) at each clock edge, rising andfalling, such that one of the data lines 413 (e.g., DAT0, DAT7, etc.)can be used to calibrate the sampling capability of the host 405. In anexample, the data lines 413 can be used to calibrate the propagationdelay between the host 405 and the eMMC 410. When intermittently usingthe data line to calibrate the propagation delay, the calibration caneither be regularly checked (e.g., at predetermined intervals, aspecific time period, number of clock cycles, read operations, etc.),checked in response to detected errors (e.g., a threshold number ofdetected errors, error rates above a threshold, etc.), or a change inconditions (e.g., temperature change, supply voltage change, etc.).

In an example, the measurement circuit 425 can determine the delay oralignment between the clock signal and the data strobe, and eitherprovide a delay to the delay circuits or other components of the host405, or provide delay or alignment information to one or more othercomponent of the host 405, such as the host processor or othercomponent. In an example, after the value of the delay is determined,the measurement circuit 425 can evaluate drift of the data strobe signalat every read operation, at regular intervals, or at one or more othertrigger conditions (e.g., detected errors, temperature, supply voltage,etc.). The measurement circuit 425 can provide drift information to oneor more other system components, such as a host processor or othercircuit, to evaluate the delay for adjustment of the delay circuits,e.g., due to drift, etc.

FIG. 5 illustrates an example portion of an eMMC system 500 including ahost 505, an eMMC 510, a communication interface including data lines(DAT[7:0]) 513 and a data strobe line (DS) 514, and sample hardware tosample a data strobe signal on the data strobe line 514. One or morecomponents illustrated in FIG. 5 can be included as part of, or separatefrom, the first sampling stage illustrated in previous figures.

In an example, the host 505 can provide a command to the eMMC 510 tobegin a high-speed mode (e.g., HS400), for example, using a commandline. In response, the eMMC 510 can provide a data strobe signal to thedata strobe line 514. The host 505 can include a data strobe inputbuffer 527 to receive a data strobe signal on the data strobe line 514from the eMMC 510, and a data strobe delay circuit 526 configured toprovide a configurable delay or one of a number of predetermined orselectable delays to the data strobe signal. In certain examples, thedata strobe delay circuit 526 (or one or more other delay circuits) canbe configured with an initial or trial value, such as beforecalibration, or according to a previous calibration or a default ornominal value. The host 505 can be configured to alter the value of thedelay of the data strobe delay circuit 526 and sample the values of thedata strobe signal across different delay values to optimize the valueof the delay of the data strobe delay circuit 526, and accordingly, thevalue of the delay for sampling data or command signals on the datalines or one or more command lines, respectively.

The host 505 can include a first input double data rate circuit (IDDR)528 configured to receive the data strobe signal and a clock signal(CLK), and, if the data strobe signal is a double data rate (DDR)signal, sample the data strobe signal on rising and falling clockcycles, and provide a value on the rising edge of the clock signal (QR)and a value on the falling edge of the clock signal (QF). In otherexamples, the system can include a delay on the clock signal instead of,or in addition to, the delay on the data strobe signal. A samplingregister 529 (e.g., a serial-to-parallel shift register) can receive theDDR data from the IDDR 528 and a clock signal (CLK), and sample a givennumber of values for a number of clock cycles, for example, in a risingedge sample register (RES) and a falling edge sample register (FES). Thesampling register can provide an output, such as one or more paralleloutputs of N samples (e.g., N being less than the number of data strobecycles in a signal data block of the eMMC 510, such as 256, etc.). In anexample, a check circuit 533 can determine if the pattern sampled by thesampling register 529 is consistent with an expected pattern, and apropagation delay, alignment, or drift between the data strobe signaland the clock signal can be determined using an output of the checkcircuit 533. In other examples, one or more other components can receivethe data strobe signal and determine, using hardware or software, thepropagation delay, alignment, or drift between the data strobe signaland the clock signal.

A control circuit 530 (e.g., control logic) can receive input from anexternal user, or from one or more other host 505 or eMMC 510 componentor process, to control one or more of the components herein. Forexample, the control circuit can control an enable circuit 531configured to enable or control one or more process or aspect of thesampling register 529. In an example, the value of the data strobesignal is a low value (“0”) until data transfer begins. Accordingly, theenable circuit 531 can monitor the output of the IDDR 528 for a highvalue (“1”) (or a number of high values or toggles) before enabling thesampling register 529.

The control circuit 530 can provide a signal to an input delay register532 configured to control a delay of the data strobe delay circuit 526.In general, the number of steps or value of steps configurable by theinput delay register 532 (or other delay register or delay circuit) canbe configured to cover at least one clock period. For example, the datastrobe delay circuit 526 can be configured with a number of possiblevalues (e.g., 32) and can cover an entire clock period (e.g., 200 MHz (5ns)). In other examples, other values or number of values can be used.Table 1 illustrates example delay taps for the data strobe delay circuit526 or the input delay register 532.

TABLE 1 Input delay codes Tap Input delay (5-bit code) Input delay (ps)0 00000 0.00 1 00001 156.25 2 00010 312.50 3 00011 468.75 4 00100 625.005 00101 781.25 6 00110 937.50 7 00111 1093.75 8 01000 1250.00 . . . . .. . . . 23 10111 3593.75 24 11000 3750.00 25 11001 3906.25 26 110104062.50 27 11011 4218.75 28 11100 4375.00 29 11101 4531.25 30 111104687.50 31 11111 4843.75

In certain examples, it can be important (such as in FPGA technology),to maintain a consistent delay across the communication interface andwithin the host 505, that the circuit path of the differentcommunication interface components are similar, such that the totaldelay added by routing the signals through the circuit paths are notsubstantially different for the information on the data lines 513 incontrast to one or more of the data strobe line 514 or one or morecommand lines (not shown). As each component and process within thecircuit has an associated delay, a similar circuit path, where possible,can be advantageous. Further, similar components within a system canprovide other benefits, such as consistent fabrication processes, and incertain examples, shared system resources or other benefits ofduplication of components or processes.

Accordingly, the host 505 can include a data input buffer 517, a datadelay circuit 516, and a second IDDR 518, similar to the components ofthe data strobe line circuit path described above, configured to sampledata signals (e.g., read data) on the data lines 513. Further, the host505 can include one or more data path circuits 519 configured to receivethe output of the second IDDR 518 and manage and provide data from thedata lines to one or more other component of the host 505. In anexample, to maintain consistent delays across the one or more commandlines or other lines of the communication interface, such circuit pathscan include similar components within the host 505. If the one or morecommand lines or other lines are not configured to receive DDR signals,an IDDR circuit can be included in the data path, but one of the twooutputs of an IDDR circuit can be ignored to maintain consistent delayswithin and across the host 505.

In other examples, the different circuit paths within the host 505(e.g., the data strobe signal path, the data line signal path, etc.) caninclude different components with substantially different delays, andthe host 505 can be configured to account for such differences byassigning different delay values to one or more delay circuits (e.g.,the data delay circuit 516, the data strobe delay circuit 527, a delaycircuit on the one or more command lines, etc.).

In certain examples, the host 505 can be configured to optimize thedelay of the data strobe signal while received data from the eMMC 510,without altering or affecting the normal operation of the data lines, asthe data strobe delay circuit 526 can be independent from, andindependently controlled with respect to one or more other delaycircuits, such as the data delay circuit 516, etc. For example, if adelay circuit (e.g., the data strobe delay circuit) has a number of tapsacross the period of the clock signal (e.g., 32), any read operation (orother operation) as long as or longer than the number of delay taps(e.g., if 32 delay taps, then 32 data blocks or more, etc.) can be usedrecalibrate, measure, or optimize the value of the delay in thebackground, while the host 505 receives data on the data lines using theprevious delay value. The check circuit 533, or one or more othercomponent, hardware or software, can determine the desired value of thedelay signal during normal data operations. In an example, thedetermined values can be compared to existing values, and, depending onthe difference (e.g., if the difference is greater than one full delaytap or otherwise above a threshold amount, in certain examples, havingrespective thresholds for each delay circuit), updated delay values canbe provided to the one or more delay circuits. In certain examples, thedelay values can be updated during data operations, at the next dataoperation, or updated at other regular or triggered intervals. The delayvalues can be evaluated using hardware or software, and such backgroundoptimization can be enabled independently from, or upon the execution ofan initial calibration. In other examples, determined values can bestored as reference amounts to compare with subsequent determinedvalues.

In other examples, the determined values or changes can be stored andreferenced in the context of data failure, such as to distinguishbetween data corruption and timing errors, or used to recover from dataerrors.

FIG. 6 illustrates an example timing diagram 600 including a clocksignal (CLK) having a period (P) (e.g., 5 ns) and rising and fallingedges, as illustrated, and different data strobe signals at differentdelay taps (e.g., DS0 through DS31, output from a data strobe delaycircuit, etc.). In this example, 32 taps cover an entire clock period.In other examples, other numbers of delays or taps can be used.

DS0 follows the clock signal by a portion of a clock period (e.g., ¼ ofa clock period, 1¼ of a clock period, 2% of a clock period, etc.). Theamount that DS0 follows the clock signal can vary, depending on, forexample, the propagation delay within or between a host and an eMMC or,in certain examples, an initial or previous delay of one or more delaycircuits. DS1 follows DS0 by single tap (e.g., 156.25 ps); DS2 followsDS1 by a single tap (e.g., 156.25 ps); etc.

As the transitions of DS0 are offset from the clock signal, such that ifthe data strobe signal is sampled over a number of clock periods (e.g.,N) at the rising and falling edges of the clock signal, the output of asampling register (e.g., the sampling register 529) of DS0 will be all“0” values at a rising edge sample register (RES), and all “1” values ata falling edge sample register (FES).

As the data strobe signal is shifted, such as by additional delay taps,the transitions on the data strobe signal will become sufficiently closeto the rising and falling edges of the clock signal, such that setup andhold time violations may occur, leading to errors in the sampled data.In this example, DS1 through DS6 are valid delay taps, with the outputof the RES and FES still consistent at “0” and “1”, respectively, overthe number of clock periods. However, at DS7 through DS9, thetransitions of the data strobe signals are sufficiently close to therising and falling edges of the clock signal such that timing violationsmay occur (e.g., violation 635), where such that the sampled values inRES and FES may not all be the same values (e.g., one or more of RES orFES will separately hold a mix of “0” and “1” over the number of clockperiods, etc.). Accordingly, in FIG. 6, DS7 through DS9 are invaliddelay taps.

In this example, DS10 through DS22 are valid delay taps, althoughwhereas the value of RES and FES in DS0 through DS6 are “0” and “1”,respectively, in DS10 through DS22, the values of RES and FES havechanged to “1” and “0”, respectively, indicating a phase change betweenthe data strobe signal and the clock signal. Further, like DS7 throughDS9, the transitions in DS23 through DS25 are sufficiently close to therising and falling edges of the clock signal such that timing violationsmay occur, and are thus invalid delay taps. DS26 through DS31 are validdelay taps with RES and FES values consistent at “0” and “1”,respectively, like in DS0 through DS6.

In an example, the RES and FES values can be checked for each delay tapat each read operation. In certain examples, such as during long readoperations, the RES and FES values can be checked in the middle of aread operation. In other examples, the RES and FES values can be checkedat regular intervals (e.g., at predetermined intervals, a specific timeperiod, number of clock cycles, read operations, etc.), checked inresponse to detected errors (e.g., a threshold number of detectederrors, error rates above a threshold, etc.), or a change in conditions(e.g., temperature change, supply voltage change, etc.). Further, theresult of the RES and FES values on the data strobe signal areindependent of any data stored on the eMMC. As such, in certainexamples, using the data strobe signal, pre-conditioning the eMMCcontent is not required to determine the value of the delay. Once thevalid and invalid delay taps are known, the time relationship betweenthe data strobe signal and the clock signal can be determined, and thevalue of the delay (e.g., of one or more of the data strobe signal, thedata signals, the clock signal, etc.) can be set.

In an example, the value of the delay can be set as one of the validdelay taps, in certain examples, at or near the midpoint of the validrange of delay taps, with a desired phase, or in the case of multipleranges of valid delay taps, at or near the midpoint of the valid rangeof delay taps having the greater number of successive valid delay taps.In FIG. 6, there are two ranges of valid delay taps, DS26 through DS6and DS10 through DS22. In an example, the widest range of valid delaytaps (e.g., the range of valid delay taps having the greatest number ofsuccessive valid taps) can be selected, and the midpoint of the widestrange of valid delay taps can be determined as the desired delay tap.

In certain examples, if the delay is adjusted multiple times, such thatthe direction of the drift can be determined, such as by a check circuitor one or more other component of the host, the value of the delay canbe set to minimize errors given the direction of drift or previousalignment. In other examples, the RES and FES values can be checkedaccording to one or more sorting or search algorithms, such as tominimize the time required to determine or estimate the valid andinvalid delay taps, or avoid checking each delay tap.

Although described herein with the hardware illustrated in FIG. 5, inother examples, one or more other hardware or software solutions can beused to determine the values of the data strobe signal at differentdelays, such as to determine the time relationship between the datastrobe signal and the clock signal.

FIG. 7 illustrates an example timing diagram 700 including a clocksignal (CLK) having a period (P) (e.g., 5 ns) and rising and fallingedges, as illustrated, and different command line signals at differentdelay taps (e.g., CMD0 through CMD31, output from a command line delaycircuit, etc.). In this example, 32 taps cover an entire clock period.In other examples, other numbers of delays or taps can be used.

The JEDEC eMMC standard provides for optional usage of the data strobesignal while receiving a command signal from the eMMC, such as on thecommand line (e.g., a command line (CMD) 111, etc.) in an enhanced datastrobe mode. After a host sends a command to the eMMC, such as using thecommand signal on the command line, the eMMC can provide a response insingle data rate (SDR) mode, which is twice as long as the data strobesignal in double data rate (DDR) mode. In an example, the rising edge ofthe clock signal can be used as the active edge. In high-speed mode withenhanced data strobe, the transitions of the command signal may occurwith the rising edge of the data strobe signal. Moreover, sampling thecommand signal can be done on the rising edges of the clock signal.

In an example, a host can include circuitry to sample command signals onone or more command lines, similar to that illustrated in FIG. 5 withrespect to sampling data signals on the data lines, including, forexample, a command input buffer, a command signal delay circuit, anIDDR, and one or more command signal path circuits. In other examples,one or more other components or hardware or software can be used todetermine a value of a delay for the command signal. For example, as thecommand signals are in SDR mode in contrast to the data strobe signal inDDR mode, but the two signals are similar, with similar circuit pathshaving similar internal delays, the value of the delay for the commandline can be selected using the determined value of the delay for thedata strobe signal.

In contrast to the data strobe signal (e.g., a DDR signal) timingdiagram 600 of FIG. 6, the command signal (e.g., an SDR signal) timingdiagram 700 of FIG. 7 has a single range of valid delay taps, CMD26through CMD22, and a single range of invalid delay taps, CMD23 throughCMD 25, where timing violations may occur (e.g., violation 735). Due tothe DDR/SDR relationship between the data strobe signal and the commandsignal, the delay for the command line can be selected as the midpointof the valid delay tap range (e.g., CMD8), which is the midpoint of thefirst invalid range from the data strobe signal timing diagram 600 ofFIG. 6. Accordingly, the value of the delay for the command line can beselected using the determined delay value for the data strobe signal.

FIG. 8 illustrates an example timing diagram 800 including a clocksignal (CLK), a data strobe signal (DS), and a command signal (CMD), incertain examples, the data strobe and command signals after having beendelayed by a delay circuit. In this example, the command signaltransitions at rising edges of the data strobe signal. In otherexamples, the command signal may transition at falling edges of theclock data strobe signal. The relationship between the data strobesignal and the command signal may be known, or detected, such as usingerror rates, rising and falling edge sampling registers, etc.

As illustrated in FIGS. 6 and 7, there are two ranges of invalid delaytaps in the data strobe signal timing diagram 600, and a single range ofinvalid delay taps in the command signal timing diagram 700. Theappropriate invalid range in the data strobe signal timing diagram 600to set the value of the delay for the command signal can be selectedusing the relationship between the data strobe signal and the commandsignal, and moreover, the values of the data strobe signal at differentdelay taps. For example, if the SDR command signal transitions at risingedges of the DDR data strobe signal, and the command signal is sampledat rising edges, the invalid range in the data strobe signal timingdiagram 600 would be that in which the value of the rising edge of theclock signal transitions from all “1” values to all “0” values, or inwhich the value of the falling edge of the clock signal transitions fromall “0” values to all “1” values. The other invalid range in the datastrobe signal timing diagram 600 is valid for the command signal timingdiagram 700.

In other examples, the command signal can be sampled using a samplingregister on rising and falling edges of the clock signal to determine adesired delay value, or a desired delay tap, such as using a midpoint ofa range of valid delay taps.

FIG. 9 illustrates an example portion of an eMMC system 900 including ahost 905, an eMMC 910, and a communication interface including a commandline (CMD) 911, a clock line (CLK) 912, a first set of data lines(DAT[6:0]) 913A, an additional data line (DAT[7]) 913B, and a datastrobe line (DS) 914. In an example, the host 905 may not have adedicated data strobe pin. The present inventors have recognized, amongother things, that data strobe functionality in such hosts can bemaintained using additional hardware between the eMMC 910 and the host905. In an example, such as in a calibration mode, one of the existingdata pins on the host can be used as a data strobe pin. With additionalhardware between the eMMC 910 and the host 905, such as a multiplexercircuit or other component, the data pin can be used as the data strobepin for calibration or determination of one or more delay values, suchas in a calibration mode, and then switched back to being used as a datapin, such as in a data read mode. The host 905 can control transitionsbetween the calibration mode (e.g., where the multiplexer circuit orother component provides the data strobe signal, or a signal consistentwith a data strobe signal (1-0-1-0 . . . ) to the host 905) and the dataread mode (e.g., where the multiplexer circuit or other componentprovides read data or a data signal to the host 905). Using anadditional hardware component to implement the data strobe feature canbe advantageous in that the data strobe features of the eMMC 910 can beused in conjunction with the host 905 without the dedicated pin withlittle to no changes in the data strobe feature of the eMMC 910.

In an example, the eMMC system 900 can include a multiplexer circuit(MUX) 945 configured to receive the additional data line 913B and thedata strobe line 914 and provide a single input to the host 905, whichmay not include a dedicated data strobe pin. In an example, themultiplexer circuit 945 can be chosen to avoid timing issues impactingsystem performance (e.g., 200 MHz DDR, etc.), and can be bidirectional,such as to communicate information from the eMMC 910 to the host 905, orfrom the host 905 to the eMMC 910. Although illustrated in FIG. 9 as thefirst set of data lines being DAT0 through DAT6, and the additional dataline as DAT7, in other examples, the data line used in combination withthe data strobe line 914 as input to the multiplexer circuit 945 caninclude any existing data line (e.g., any one or more of DAT[0:7]). Inan example, the selection of the additional data line 913B can bedetermined by a printed circuit board designer, in certain examples, inaccordance with data path balance, or one or more other designconsiderations. Using the multiplexer circuit 945, the eMMC system 900can implement the delay calibration procedures described herein,including determining an optimal delay value for each of one or moredelay circuits in the eMMC system 900, such as a data delay circuit 916.

The host 905 can include a first sampling stage circuit (FSS) 915 orother sampling circuit configured to sample data on the first set ofdata lines 913A and the output of the multiplexer circuit 945, includingdata from the additional data line 913B and the data strobe line 914.The host 905 can include a clock generator circuit (CKGEN) 920configured to provide a clock signal to the eMMC 910 using the clockline 912, and a host control circuit (CTRL) 940 configured to controlone or more host processes. In an example, the host control circuit 940can send or receive commands to or from the eMMC 910, perform operationsor instructions, or communicate or control one or more other componentof the eMMC system 900, including in certain examples, the multiplexercircuit 945, such as using one or more generic input/output (I/O) pins.

From a hardware standpoint, only the addition of the multiplexer circuit945 and the connection of the multiplexer circuit 945 to the host 905(e.g., using general-purpose 1/O, etc.) are required to implement thedata strobe features in an eMMC system 900 having a host 905 without adedicated data strobe pin. The hardware of the host 905 and the eMMC 910can remain unchanged. In certain examples, the additional changesrequired to implement the data strobe feature can be made in software ofthe eMMC system 900.

As the host 905 provides command signals to the eMMC 910 (and receivescommand signal from the eMMC 910), the host 905 is generally aware whento expect data from the eMMC 910 over the communication interface. Theselection of the multiplexer circuit 945 can be done synchronous withdata transfer, taking into account that in normal data strobe operation,the data strobe signal is only working when the eMMC 910 is providingdata to the host 905. Accordingly, measurement of the delay between thehost 905 and the eMMC 910, or calibration of the clock signal to thedata, data strobe, or command signals, can be provided at various times,in certain examples, alternating with read or other operations. In anexample, the process can be implemented in phases. For example, thevalue of the data delay circuit 916 can be set for each possible delayvalue (e.g., 32 delay values, or one or more other delay values over aperiod of the clock signal). The received data can be processed toidentify the data strobe signal. The results can be evaluated, and theoptimal delay value can be determined or selected. Then the determinedor selected delay value can be applied to the data lines, such as usingthe data delay circuit 916 or one or more other delay circuits (e.g.,including one or more other delay circuits on one or more other lines ofthe communication interface).

In an example, the control circuit 940 can control the multiplexercircuit 945, switching between the data signal and the data strobesignal. The data strobe signal can be sampled, such as using one or moreof the circuits or methods described here, for example, with respect tothe internal host clock, such as from the clock generator circuit 920.The delay applied to the data strobe signal (e.g., using the data delaycircuit 916) can be changed, with the results of the sampling storedaccording to the applied delay. The results can be evaluated, and theoptimal delay value can be selected (e.g., such that the valid range ofdelay taps is as wide as possible around the sampling edges) and appliedto one or more lines of the communication interface, including one ormore of the data lines 913A, the additional data line 913B, the datastrobe line 914, the command line 911, etc.

In an example, the host 905 can determine or calibrate the optimal delayvalue using a data strobe signal through the multiplexer circuit 945 inresponse to a read command in high-speed mode from the eMMC 910. In anexample, the host 905 can request the read command from the eMMC 910 todetermine the optimal delay value, and as such, the sampled data valueson the first set of data lines 913A can be ignored. After sending theread command, the host 905 can wait for a start bit on the data lines.The absence of a start bit can lead to a timeout of the read command. Inan example, the data line used to recognize the start bit should not beused as the additional data line to be multiplexed with the data strobeline, such as to avoid misdetection of the start bit. Further, it ispossible to invert the data strobe signal in the eMMC 910, or betweenthe eMMC 910 and the multiplexer circuit 945, before routing the datastrobe signal to the multiplexer circuit 945. Once the delay value isdetermined or calibrated, the multiplexer circuit 945 can switch to theadditional data line 913B, and the first sampling stage 915 can read andsample requested data. In an example, the first sampling stage 915 caninclude components such as illustrated in FIG. 5.

FIG. 10 illustrates a block diagram of an example machine 1000 uponwhich any one or more of the techniques (e.g., methodologies) discussedherein may perform, such as triggering a CSAVE operation in a memorydevice (e.g., an NVDIMM) using a timer implemented using a memorycontroller of the NVDIMM. In alternative embodiments, the machine 1000may operate as a standalone device or may be connected (e.g., networked)to other machines. In a networked deployment, the machine 1000 mayoperate in the capacity of a server machine, a client machine, or bothin server-client network environments. In an example, the machine 1000may act as a peer machine in peer-to-peer (P2P) (or other distributed)network environment. The machine 1000 may be a personal computer (PC), atablet PC, a set-top box (STB), a personal digital assistant (PDA), amobile telephone, a web appliance, an IoT device, automotive system, orany machine capable of executing instructions (sequential or otherwise)that specify actions to be taken by that machine. Further, while only asingle machine is illustrated, the term “machine” shall also be taken toinclude any collection of machines that individually or jointly executea set (or multiple sets) of instructions to perform any one or more ofthe methodologies discussed herein, such as cloud computing, software asa service (SaaS), other computer cluster configurations.

Examples, as described herein, may include, or may operate by, logic,components, devices, packages, or mechanisms. Circuitry is a collection(e.g., set) of circuits implemented in tangible entities that includehardware (e.g., simple circuits, gates, logic, etc.). Circuitrymembership may be flexible overtime and underlying hardware variability.Circuitries include members that may, alone or in combination, performspecific tasks when operating. In an example, hardware of the circuitrymay be immutably designed to carry out a specific operation (e.g.,hardwired). In an example, the hardware of the circuitry may includevariably connected physical components (e.g., execution units,transistors, simple circuits, etc.) including a computer-readable mediumphysically modified (e.g., magnetically, electrically, moveableplacement of invariant massed particles, etc.) to encode instructions ofthe specific operation. In connecting the physical components, theunderlying electrical properties of a hardware constituent are changed,for example, from an insulator to a conductor or vice versa. Theinstructions enable participating hardware (e.g., the execution units ora loading mechanism) to create members of the circuitry in hardware viathe variable connections to carry out portions of the specific taskswhen in operation. Accordingly, the computer-readable medium iscommunicatively coupled to the other components of the circuitry whenthe device is operating. In an example, any of the physical componentsmay be used in more than one member of more than one circuitry. Forexample, under operation, execution units may be used in a first circuitof a first circuitry at one point in time and reused by a second circuitin the first circuitry, or by a third circuit in a second circuitry at adifferent time.

The machine (e.g., computer system) 1000 (e.g., the host 105, the NVDIMM110, etc.) may include a hardware processor 1002 (e.g., a centralprocessing unit (CPU), a graphics processing unit (GPU), a hardwareprocessor core, or any combination thereof, such as a memory controller,etc.), a main memory 1004 and a static memory 1006, some or all of whichmay communicate with each other via an interlink (e.g., bus) 1008. Themachine 1000 may further include a display unit 1010, an alphanumericinput device 1012 (e.g., a keyboard), and a user interface (UI)navigation device 1014 (e.g., a mouse). In an example, the display unit1010, input device 1012 and UI navigation device 1014 may be a touchscreen display. The machine 1000 may additionally include a signalgeneration device 1018 (e.g., a speaker), a network interface device1020, and one or more sensors 1016, such as a global positioning system(GPS) sensor, compass, accelerometer, or other sensor. The machine 1000may include an output controller 1028, such as a serial (e.g., universalserial bus (USB), parallel, or other wired or wireless (e.g., infrared(IR), near field communication (NFC), etc.) connection to communicate orcontrol one or more peripheral devices (e.g., a printer, card reader,etc.).

The machine 1000 may include a machine-readable medium 1022 on which isstored one or more sets of data structures or instructions 1024 (e.g.,software) embodying or utilized by any one or more of the techniques orfunctions described herein. The instructions 1024 may also reside,completely or at least partially, within the main memory 1004, withinstatic memory 1006, or within the hardware processor 1002 duringexecution thereof by the machine 1000. In an example, one or anycombination of the hardware processor 1002, the main memory 1004, thestatic memory 1006, or the mass storage 1021 may constitute themachine-readable medium 1022.

While the machine-readable medium 1022 is illustrated as a singlemedium, the term “machine-readable medium” may include a single mediumor multiple media (e.g., a centralized or distributed database, orassociated caches and servers) configured to store the one or moreinstructions 1024.

The term “machine-readable medium” may include any medium that iscapable of storing, encoding, or carrying instructions for execution bythe machine 1000 and that cause the machine 1000 to perform any one ormore of the techniques of the present disclosure, or that is capable ofstoring, encoding, or carrying data structures used by or associatedwith such instructions. Non-limiting machine-readable medium examplesmay include solid-state memories, and optical and magnetic media. In anexample, a massed machine-readable medium comprises a machine-readablemedium with a plurality of particles having invariant (e.g., rest) mass.Accordingly, massed machine-readable media are not transitorypropagating signals. Specific examples of massed machine-readable mediamay include: non-volatile memory, such as semiconductor memory devices(e.g., Electrically Programmable Read-Only Memory (EPROM), ElectricallyErasable Programmable Read-Only Memory (EEPROM)) and flash memorydevices; magnetic disks, such as internal hard disks and removabledisks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions 1024 (e.g., software, programs, an operating system(OS), etc.) or other data are stored on the storage device 1021, can beaccessed by the memory 1004 for use by the processor 1002. The memory1004 (e.g., DRAM) is typically fast, but volatile, and thus a differenttype of storage than the storage device 1021 (e.g., an SSD), which issuitable for long-term storage, including while in an “off” condition.The instructions 1024 or data in use by a user or the machine 1000 aretypically loaded in the memory 1004 for use by the processor 1002. Whenthe memory 1004 is full, virtual space from the storage device 1021 canbe allocated to supplement the memory 1004; however, because the storage1021 device is typically slower than the memory 1004, and write speedsare typically at least twice as slow as read speeds, use of virtualmemory can greatly reduce user experience due to storage device latency(in contrast to the memory 1004, e.g., DRAM). Further, use of thestorage device 1021 for virtual memory can greatly reduce the usablelifespan of the storage device 1021.

In contrast to virtual memory, virtual memory compression (e.g., theLinux™ kernel feature “ZRAM”) uses part of the memory as compressedblock storage to avoid paging to the storage device 1021. Paging takesplace in the compressed block until it is necessary to write such datato the storage device 1021. Virtual memory compression increases theusable size of memory 1004, while reducing wear on the storage device1021.

Storage devices optimized for mobile electronic devices, or mobilestorage, traditionally include MMC solid-state storage devices (e.g.,micro Secure Digital (microSD™) cards, etc.). MMC devices include anumber of parallel interfaces (e.g., an 8-bit parallel interface) with ahost device, and are often removable and separate components from thehost device. In contrast, eMMC™ devices are attached to a circuit boardand considered a component of the host device, with read speeds thatrival serial ATA™ (Serial AT (Advanced Technology) Attachment, or SATA)based SSD devices. However, demand for mobile device performancecontinues to increase, such as to fully enable virtual oraugmented-reality devices, utilize increasing networks speeds, etc. Inresponse to this demand, storage devices have shifted from parallel toserial communication interfaces. Universal Flash Storage (UFS) devices,including controllers and firmware, communicate with a host device usinga low-voltage differential signaling (LVDS) serial interface withdedicated read/write paths, further advancing greater read/write speeds.

The instructions 1024 may further be transmitted or received over acommunications network 1026 using a transmission medium via the networkinterface device 1020 utilizing any one of a number of transferprotocols (e.g., frame relay, internet protocol (IP), transmissioncontrol protocol (TCP), user datagram protocol (UDP), hypertext transferprotocol (HTTP), etc.). Example communication networks may include alocal area network (LAN), a wide area network (WAN), a packet datanetwork (e.g., the Internet), mobile telephone networks (e.g., cellularnetworks), Plain Old Telephone (POTS) networks, and wireless datanetworks (e.g., Institute of Electrical and Electronics Engineers (IEEE)802.11 family of standards known as Wi-Fi®, IEEE 802.16 family ofstandards known as WiMax®), IEEE 802.15.4 family of standards,peer-to-peer (P2P) networks, among others. In an example, the networkinterface device 1020 may include one or more physical jacks (e.g.,Ethernet, coaxial, or phone jacks) or one or more antennas to connect tothe communications network 1026. In an example, the network interfacedevice 1020 may include a plurality of antennas to wirelesslycommunicate using at least one of single-input multiple-output (SIMO),multiple-input multiple-output (MIMO), or multiple-input single-output(MISO) techniques. The term “transmission medium” shall be taken toinclude any intangible medium that is capable of storing, encoding, orcarrying instructions for execution by the machine 1000, and includesdigital or analog communications signals or other intangible medium tofacilitate communication of such software.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples”. Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” may include “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In the appended claims, the terms “including” and“in which” are used as the plain-English equivalents of the respectiveterms “comprising” and “wherein”. Also, in the following claims, theterms “including” and “comprising” are open-ended. A system, device,article, or process that includes elements in addition to those listedafter such a term in a claim are still deemed to fall within the scopeof that claim. Moreover, in the following claims, the terms “first,”“second,” and “third,” etc. are used merely as labels, and are notintended to impose numerical requirements on their objects.

In various examples, the components, controllers, processors, units,engines, or tables described herein can include, among other things,physical circuitry or firmware stored on a physical device. As usedherein, “processor” means any type of computational circuit such as, butnot limited to, a microprocessor, a microcontroller, a graphicsprocessor, a digital signal processor (DSP), or any other type ofprocessor or processing circuit, including a group of processors ormulti-core devices.

Operating a memory cell, as used herein, includes reading from, writingto, or erasing the memory cell. The operation of placing a memory cellin an intended state is referred to herein as “programming,” and caninclude both writing to or erasing from the memory cell (e.g., thememory cell may be programmed to an erased state).

According to one or more embodiments of the present disclosure, a memorycontroller (e.g., a processor, controller, firmware, etc.) locatedinternal or external to a memory device, is capable of determining(e.g., selecting, setting, adjusting, computing, changing, clearing,communicating, adapting, deriving, defining, utilizing, modifying,applying, etc.) a quantity of wear cycles, or a wear state (e.g.,recording wear cycles, counting operations of the memory device as theyoccur, tracking the operations of the memory device it initiates,evaluating the memory device characteristics corresponding to a wearstate, etc.)

According to one or more embodiments of the present disclosure, a memoryaccess device may be configured to provide wear cycle information to thememory device with each memory operation. The memory device controlcircuitry (e.g., control logic) may be programmed to compensate formemory device performance changes corresponding to the wear cycleinformation. The memory device may receive the wear cycle informationand determine one or more operating parameters (e.g., a value,characteristic) in response to the wear cycle information.

It will be understood that when an element is referred to as being “on,”“connected to” or “coupled with” another element, it can be directly on,connected, or coupled with the other element or intervening elements maybe present. In contrast, when an element is referred to as being“directly on,” “directly connected to” or “directly coupled with”another element, there are no intervening elements or layers present. Iftwo elements are shown in the drawings with a line connecting them, thetwo elements can be either be coupled, or directly coupled, unlessotherwise indicated.

Method examples described herein can be machine, device, orcomputer-implemented at least in part. Some examples can include acomputer-readable medium, a device-readable medium, or amachine-readable medium encoded with instructions operable to configurean electronic device to perform methods as described in the aboveexamples. An implementation of such methods can include code, such asmicrocode, assembly language code, a higher-level language code, or thelike. Such code can include computer readable instructions forperforming various methods. The code may form portions of computerprogram products. Further, the code can be tangibly stored on one ormore volatile or non-volatile tangible computer-readable media, such asduring execution or at other times. Examples of these tangiblecomputer-readable media can include, but are not limited to, hard disks,removable magnetic disks, removable optical disks (e.g., compact discsand digital video disks), magnetic cassettes, memory cards or sticks,random access memories (RAMs), read only memories (ROMs), solid statedrives (SSDs), Universal Flash Storage (UFS) device, embedded MMC (eMMC)device, and the like.

An example (e.g., “Example 1”) of subject matter (e.g., a system) caninclude a host device; and a multiplexer circuit configured to receive adata signal and a data strobe signal from an embedded MultiMediaCard(eMMC) device, and to selectively provide one of the data signal or thedata strobe signal to a data pin of the host device, wherein the hostdevice is configured to receive an output of the multiplexer circuit ata data pin of the host device, and to determine a timing relationshipbetween the data strobe signal received from the multiplexer circuit atthe data pin and an internal clock signal.

In Example 2, the subject matter of Example 1 can optionally beconfigured such that the host device is configured to control themultiplexer circuit, the multiplexer circuit is configured to providethe data signal at the output in a data read mode, and the data strobesignal at the output in a calibration mode, and the host device isconfigured to receive the data strobe signal from the multiplexercircuit in the calibration mode, and to determine the timingrelationship between the data strobe signal received from themultiplexer circuit at the data pin and the internal clock signal in thecalibration mode.

In Example 3, the subject matter of any one or more of Examples 1-2 canoptionally be configured such that the host device includes: a delaycircuit configured to delay the received output of the multiplexercircuit from the data pin by a configurable delay value; and a samplingcircuit configured to sample the output of the multiplexer circuit at atransition of the internal clock signal, wherein the host device isconfigured to adjust the delay value of the delay circuit using thedetermined timing relationship to align the output of the multiplexercircuit and the internal clock signal for sampling.

In Example 4, the subject matter of any one or more of Examples 1-3 canoptionally be configured such that the host device includes: a delaycircuit configured to delay the received output of the multiplexercircuit from the data pin by a configurable delay value; and a samplingcircuit configured to sample the output of the multiplexer circuit at atransition of the internal clock signal, wherein the host device isconfigured to adjust the delay value of the delay circuit, and to samplethe output of the multiplexer circuit at different delay values todetermine an alignment between the output of the multiplexer circuit andthe internal clock signal.

In Example 5, the subject matter of any one or more of Examples 1-4 canoptionally be configured such that the host device includes a set ofdata pins, wherein the data pin is one of the set of data pins and thehost device does not include a dedicated data strobe pin.

In Example 6, the subject matter of any one or more of Examples 1-5 canoptionally be configured to include the eMMC device including a data pincorresponding to the data pin of the host device and a dedicated datastrobe pin configured to provide the data strobe signal in a high-speedmode, wherein the multiplexer circuit includes: a first input coupled toa data pin of the eMMC device configured to receive read data from theeMMC device; a second input coupled to a data strobe pin of the eMMCdevice configured to receive the data strobe signal from the eMMCdevice; an output coupled to a corresponding data pin of the hostdevice; and a control input coupled to a general-purpose input/output(GPIO) pin of the host device.

In Example 7, the subject matter of any one or more of Examples 1-6 canoptionally be configured such that, in a calibration mode, the hostdevice is configured to: provide a control signal to the multiplexercircuit using the GPIO pin to couple the data strobe pin of the eMMCdevice to the output of the multiplexer circuit; provide a read commandto the eMMC device configured to trigger the eMMC device to provide thedata strobe signal on the data strobe pin; receive the data strobesignal from the multiplexer circuit at the data pin of the host device;and determine the timing relationship between the data strobe signalreceived at the data pin of the host device from the multiplexercircuit.

In Example 8, the subject matter of any one or more of Examples 1-7 canoptionally be configured such that, in a data read mode, the host deviceis configured to: provide a control signal to the multiplexer circuitusing the GPIO pin to couple the data pin of the eMMC device to theoutput of the multiplexer circuit; provide a read command to the eMMCdevice; and receive read data from the multiplexer circuit at the datapin of the host device.

In Example 9, the subject matter of any one or more of Examples 1-8 canoptionally be configured such that, in the data read mode, themultiplexer circuit is configured to receive the data strobe signal fromthe eMMC device, but is not configured to provide the data strobe signalto the host device.

In Example 10, the subject matter of any one or more of Examples 1-9 canoptionally be configured such that the host device is configured tointermittently trigger the calibration mode to determine the timingrelationship between the data strobe signal and the internal clocksignal, and to control a delay value of a delay circuit using thedetermined timing relationship.

An example (e.g., “Example 11”) of subject matter (e.g., a method) caninclude: receiving a data signal and a data strobe signal at a hostdevice from an embedded MultiMediaCard (eMMC) device at a multiplexercircuit; selectively providing, using the multiplexer circuit, one ofthe data signal or the data strobe signal to a data pin of the hostdevice; receiving an output of the multiplexer circuit at a data pin ofthe host device; and determining, using the host device, a timingrelationship between the data strobe signal received from themultiplexer circuit at the data pin and an internal clock signal tocontrol a delay circuit of the host device.

In Example 12, the subject matter of Example 11 can optionally beconfigured to include controlling the multiplexer circuit using the hostdevice to provide the data signal at the output in a data read mode, andthe data strobe signal at the output in a calibration mode; receivingthe data strobe signal from the multiplexer circuit at the host devicein the calibration mode; and wherein determining the timing relationshipbetween the data strobe signal received from the multiplexer circuit atthe data pin and the internal clock signal includes in determining thetiming relationship in the calibration mode.

In Example 13, the subject matter of any one or more of Examples 11-12can optionally be configured to include delaying the received output ofthe multiplexer circuit from the data pin by a configurable delay valueusing a delay circuit in the host device; sampling the output of themultiplexer circuit at a transition of the internal clock signal using asampling circuit in the host device; adjusting, using the host device,the delay value of the delay circuit using the determined timingrelationship to align the output of the multiplexer circuit and theinternal clock signal for sampling.

In Example 14, the subject matter of any one or more of Examples 11-13can optionally be configured to include delaying the received output ofthe multiplexer circuit from the data pin of the host device by aconfigurable delay value using a delay circuit in the host device;adjusting, using the host device, the delay value of the delay circuit;and sampling the output of the multiplexer circuit at a transition ofthe internal clock signal using a sampling circuit in the host device atdifferent delay values to determine an alignment between the output ofthe multiplexer circuit and the internal clock signal.

In Example 15, the subject matter of any one or more of Examples 11-14can optionally be configured such that the host device does not includea dedicated data strobe pin.

In Example 16, the subject matter of any one or more of Examples 11-15can optionally be configured to include providing the data strobe signalat the data strobe pin of the eMMC device in response to a read requestin a high-speed mode of the eMMC device; receiving read data from theeMMC device at a first input of the multiplexer circuit; receiving thedata strobe signal from the eMMC device in the high-speed mode at asecond input of the multiplexer circuit; controlling an output of themultiplexer circuit using a general-purpose input/output (GPIO) pin ofthe host device.

In Example 17, the subject matter of any one or more of Examples 11-16can optionally be configured to include, in a calibration mode of thehost device: providing a control signal to the multiplexer circuit usingthe GPIO pin to couple the data strobe pin of the eMMC device to theoutput of the multiplexer circuit; providing a read command to the eMMCdevice to trigger the eMMC device to provide the data strobe signal onthe data strobe pin; receiving the data strobe signal from themultiplexer circuit at the data pin of the host device; and determiningthe timing relationship between the data strobe signal received at thedata pin of the host device from the multiplexer circuit.

In Example 18, the subject matter of any one or more of Examples 11-17can optionally be configured to include, in a data read mode of the hostdevice: providing a control signal to the multiplexer circuit using theGPIO pin to couple the data pin of the eMMC device to the output of themultiplexer circuit; providing a read command to the eMMC device totrigger the eMMC device to provide read data to the data pin; andreceiving read data from the multiplexer circuit at the data pin of thehost device.

In Example 19, the subject matter of any one or more of Examples 11-18can optionally be configured to include, in the data read mode:receiving the data strobe signal from the eMMC device at the multiplexercircuit, but not providing the data strobe signal to the host device.

In Example 20, the subject matter of any one or more of Examples 11-19can optionally be configured to include intermittently triggering, usingthe host device, the calibration mode to determine the timingrelationship between the data strobe signal and the internal clocksignal, and controlling, using the host device, a delay value of a delaycircuit using the determined timing relationship.

An example (e.g., “Example 21”) of subject matter (e.g., a system) caninclude: a host device configured to receive read data from an embeddedMultiMediaCard (eMMC) device over data lines of a communicationinterface and a data strobe signal from the eMMC device over a datastrobe line of the communication interface, wherein the host device isconfigured to determine a timing relationship between the data strobesignal and an internal clock signal to align the read data for sampling.

In Example 22, the subject matter of Example 21 can optionally beconfigured such that the host device is configured to determine thetiming relationship between the data strobe signal and the internalclock signal in a calibration mode to align the read data for sampling,and the host device is configured to receive read data from the eMMCdevice over the data strobe line in a data mode separate fromcalibration mode.

In Example 23, the subject matter of any one or more of Examples 21-22can optionally be configured such that the host device includes: datapins configured to receive read data from the eMMC device over the datalines of the communication interface; and a data strobe pin configuredto receive the data strobe signal from the eMMC device over a datastrobe line of the communication interface, wherein the host device isconfigured to receive read data from the eMMC device over at the datapins in both the calibration mode and the data mode.

In Example 24, the subject matter of any one or more of Examples 21-23can optionally be configured such that the host device is configured toprovide a command to the eMMC device to provide read data over the datastrobe line of the communication interface in the data mode.

In Example 25, the subject matter of any one or more of Examples 21-24can optionally be configured such that the data pins consist of a number(N) of data pins, and the host is configured to receive read data fromthe eMMC device using the N data pins and the data strobe pin,collectively N+1 pins, in the data mode.

In Example 26, the subject matter of any one or more of Examples 1-25can optionally be configured such that a data delay circuit configuredto delay the received read data in the host device by a configurabledelay value; and a sampling circuit configured to sample the read dataat a transition of the internal clock signal, wherein the host device isconfigured to adjust the delay value of the data delay circuit using thedetermined timing relationship to align the read data and the internalclock signal for sampling.

In Example 27, the subject matter of any one or more of Examples 21-26can optionally be configured such that a data strobe delay circuitconfigured to delay the received data strobe signal by a configurabledelay value; and a measurement circuit configured to determine thetiming relationship between the data strobe signal and the internalclock signal, wherein the host device is configured to adjust the delayvalue of the data strobe delay circuit using the determined timingrelationship.

In Example 28, the subject matter of any one or more of Examples 21-27can optionally be configured such that a data strobe delay circuitconfigured to delay the received data strobe signal by a configurabledelay value, wherein the host device is configured to adjust the delayvalue of the data strobe delay circuit, and to sample the data strobesignal at different delay values to determine the timing relationshipbetween the data strobe signal and the internal clock signal.

In Example 29, the subject matter of any one or more of Examples 21-28can optionally be configured such that the host device is configured totrigger determination of the timing relationship.

An example (e.g., “Example 30”) of subject matter (e.g., a method) caninclude: receiving read data at a host device from an embeddedMultiMediaCard (eMMC) device over data lines of a communicationinterface; receiving a data strobe signal at the host device from theeMMC device over a data strobe line of the communication interface; anddetermining, using the host device, a timing relationship between thedata strobe signal and an internal clock signal to align the read datafor sampling.

In Example 31, the subject matter of Example 30 can optionally beconfigured to include determining the timing relationship between thedata strobe signal and the internal clock signal using the host devicein a calibration mode to align the read data for sampling; and receivingread data from the eMMC device over the data strobe line using the hostdevice in a data mode separate from calibration mode.

In Example 32, the subject matter of any one or more of Examples 30-31can optionally be configured such that receiving read data at the hostdevice includes receiving read data from the eMMC device over the datalines of the communication interface at data pins of the host device inboth the calibration mode and the data mode, and receiving the datastrobe signal includes receiving the data strobe signal from the eMMCdevice over a data strobe line of the communication interface at a datastrobe pin.

In Example 33, the subject matter of any one or more of Examples 32 canoptionally be configured to include providing a command to the eMMCdevice, using the host device, to provide read data over the data strobeline of the communication interface in the data mode.

In Example 34, the subject matter of any one or more of Examples 30-33can optionally be configured such that the data pins consist of a number(N) of data pins, and wherein receiving read data from the eMMC deviceincludes using the N data pins and the data strobe pin, collectively N+1pins, in the data mode.

In Example 35, the subject matter of any one or more of Examples 30-34can optionally be configured to include: delaying the received read datain the host device by a configurable delay value using a data delaycircuit; sampling the read data at a transition of the internal clocksignal using a sampling circuit; and adjusting, using the host device,the delay value of the data delay circuit using the determined timingrelationship to align the read data and the internal clock signal forsampling.

In Example 36, the subject matter of any one or more of Examples 30-35can optionally be configured to include: delaying the received datastrobe signal by a configurable delay value using a data strobe delaycircuit; determining the timing relationship between the data strobesignal and the internal clock signal using a measurement circuit; andadjusting, using the host device, the delay value of the data strobedelay circuit using the determined timing relationship.

In Example 37, the subject matter of any one or more of Examples 30-36can optionally be configured to include: delaying the received datastrobe signal by a configurable delay value using a data strobe delaycircuit; adjusting the delay value of the data strobe delay circuitusing the host device; and sampling the data strobe signal at differentdelay values to determine the timing relationship between the datastrobe signal and the internal clock signal using the host device.

In Example 38, the subject matter of any one or more of Examples 30-37can optionally be configured to include triggering determination of thetiming relationship using the host device.

An example (e.g., “Example 39”) of subject matter (e.g., a devicereadable storage medium) can provide instructions that, when executed bya controller of a host device cause the controller to perform operationscomprising: receive read data from an embedded MultiMediaCard (eMMC)device over data lines of a communication interface; receive a datastrobe signal at the host device from the eMMC device over a data strobeline of the communication interface; and determining a timingrelationship between the data strobe signal and an internal clock signalto align the read data for sampling.

In Example 40, the subject matter of Example 39 can optionally beconfigured such that determining the timing relationship includes:determine the timing relationship between the data strobe signal and theinternal clock signal using the host device in a calibration mode toalign the read data for sampling; and receive read data from the eMMCdevice over the data strobe line using the host device in a data modeseparate from calibration mode.

Example 41 is an apparatus comprising respective means for performingany of the methods or techniques of Examples 1-40.

Example 42 is a system, apparatus, or device to perform the operationsof any of Examples 1-41.

Example 43 is a tangible machine-readable medium embodying instructionsto perform or implement the operations of any of Examples 1-42.

Example 44 is a method to perform the operations of any of Examples1-43.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment, and it is contemplated that such embodiments can be combinedwith each other in various combinations or permutations. The scope ofthe invention should be determined with reference to the appendedclaims, along with the full scope of equivalents to which such claimsare entitled.

1. (canceled)
 2. A system comprising: a host device; and a multiplexercircuit configured to receive a data signal and a data strobe signalfrom an embedded MultiMediaCard (eMMC) device, and to selectivelyprovide one of the data signal or the data strobe signal to a data pinof the host device, wherein the host device is configured to receive anoutput of the multiplexer circuit at the data pin of the host device,and wherein the host device is configured to: determine a timingrelationship between the data strobe signal received from themultiplexer circuit at the data pin of the host device and an internalclock signal in a calibration mode; and control sampling of the datasignal received from the multiplexer circuit at the data pin of the hostdevice using the determined timing relationship in a data read mode. 3.The system of claim 2, wherein the data pin is one of a set of data pins(DAT[N:0]), wherein N is a positive integer.
 4. The system of claim 3,wherein the host device includes: a command pin (CMD); a clock pin(CLK); a general-purpose input/output (GPIO) pin; and the data pin, andwherein the host device does not include a dedicated data strobe pin. 5.The system of claim 2, wherein the host device is configured to: providea command to the eMMC device to provide the data strobe signal on thedata strobe pin of the eMMC device; provide a control signal, separatefrom the command to the eMMC device, to the multiplexer circuit toprovide the data strobe signal from the eMMC device at the output of themultiplexer circuit; and receive the data strobe signal from the outputof the multiplexer circuit at the data pin of the host device, whereinthe multiplexer circuit is separate from the eMMC device.
 6. The systemof claim 2, wherein the host device includes: a delay circuit configuredto delay the received output of the multiplexer circuit from the datapin by a configurable delay value; and a sampling circuit configured tosample the output of the multiplexer circuit at a transition of theinternal clock signal, wherein, to determine the timing relationship inthe calibration mode, the host device is configured to adjust the delayvalue of the delay circuit and to sample the output of the multiplexercircuit at different delay values to determine an alignment between theoutput of the multiplexer circuit and the internal clock signal.
 7. Thesystem of claim 2, including the eMMC device, wherein the data pin ofthe eMMC device is coupled to the data pin of the host device and theeMMC device includes a dedicated data strobe pin configured to providethe data strobe signal in a high-speed mode, and wherein the multiplexercircuit includes: a first input coupled to the data pin of the eMMCdevice configured to receive read data from the eMMC device; a secondinput coupled to the data strobe pin of the eMMC device configured toreceive the data strobe signal from the eMMC device; an output coupledto the data pin of the host device; and a control input coupled to ageneral-purpose input/output (GPIO) pin of the host device.
 8. Thesystem of claim 2, wherein, in the calibration mode, the host device isconfigured to: provide a control signal to the multiplexer circuit usinga general-purpose input/output (GPIO) pin of the host device; andprovide a read command to the eMMC device configured to trigger the eMMCdevice to provide the data strobe signal on the data strobe pin of theeMMC device.
 9. The system of claim 8, wherein, in the data read mode,the host device is configured to: provide a control signal to themultiplexer circuit using the GPIO pin to couple the data pin of theeMMC device to the output of the multiplexer circuit; provide a readcommand to the eMMC device; and receive read data from the multiplexercircuit at the data pin of the host device.
 10. The system of claim 8,wherein, in the data read mode, the multiplexer circuit is configured toreceive the data strobe signal from the eMMC device, but is notconfigured to provide the data strobe signal to the host device, whereinthe eMMC device includes a dedicated data strobe pin, and wherein thehost device does not include a dedicated data strobe pin.
 11. The systemof claim 2, wherein the host device is configured to intermittentlytrigger the calibration mode to determine the timing relationshipbetween the data strobe signal and the internal clock signal, and tocontrol a delay value of a delay circuit using the determined timingrelationship.
 12. A method comprising: receiving, at a multiplexercircuit, a data signal and a data strobe signal from an embeddedMultiMediaCard (eMMC) device, and selectively providing, using themultiplexer circuit, one of the data signal or the data strobe signal toa data pin of a host device; determining, using the host device, atiming relationship between the data strobe signal received from themultiplexer circuit at the data pin of the host device and an internalclock signal in a calibration mode; and controlling, using the hostdevice, sampling of the data signal received from the multiplexercircuit at the data pin of the host device using the determined timingrelationship in a data read mode.
 13. The method of claim 12, whereinthe data pin is one of a set of data pins (DAT[N:0]), wherein N is apositive integer.
 14. The method of claim 13, wherein the host deviceincludes: a command pin (CMD); a clock pin (CLK); a general-purposeinput/output (GPIO) pin; and the data pin, and wherein the host devicedoes not include a dedicated data strobe pin.
 15. The method of claim12, comprising: providing, using the host device, a command to the eMMCdevice to provide the data strobe signal on the data strobe pin of theeMMC device; providing, using the host device, a control signal,separate from the command to the eMMC device, to the multiplexer circuitto provide the data strobe signal from the eMMC device at the output ofthe multiplexer circuit; and receiving the data strobe signal from theoutput of the multiplexer circuit at the data pin of the host device,wherein the multiplexer circuit is separate from the eMMC device. 16.The method of claim 12, comprising: delaying the received output of themultiplexer circuit from the data pin by a configurable delay valueusing a delay circuit; and sampling the output of the multiplexercircuit at a transition of the internal clock signal using a samplingcircuit, wherein determining the timing relationship in the calibrationmode comprises adjusting the delay value of the delay circuit andsampling the output of the multiplexer circuit at different delay valuesto determine an alignment between the output of the multiplexer circuitand the internal clock signal.
 17. The method of claim 12, wherein thedata pin of the eMMC device is coupled to the data pin of the hostdevice and the eMMC device includes a dedicated data strobe pinconfigured to provide the data strobe signal in a high-speed mode,wherein the method includes: receiving read data from the eMMC deviceusing a first input of the multiplexer circuit coupled to the data pinof the eMMC device; and receiving the data strobe signal from the eMMCdevice using a second input of the multiplexer circuit coupled to thedata strobe pin of the eMMC device, and wherein the multiplexer circuitincludes: an output coupled to the data pin of the host device; and acontrol input coupled to a general-purpose input/output (GPIO) pin ofthe host device.
 18. The method of claim 12, comprising, in thecalibration mode, using the host device: providing a control signal tothe multiplexer circuit using a general-purpose input/output (GPIO) pinof the host device; and providing a read command to the eMMC deviceconfigured to trigger the eMMC device to provide the data strobe signalon the data strobe pin of the eMMC device.
 19. The method of claim 18,comprising, in the data read mode, using the host device: providing acontrol signal to the multiplexer circuit using the GPIO pin to couplethe data pin of the eMMC device to the output of the multiplexercircuit; providing a read command to the eMMC device; and receiving readdata from the multiplexer circuit at the data pin of the host device.20. The method of claim 18, comprising, in the data read mode: receivingthe data strobe signal from the eMMC device using the multiplexercircuit, but not providing the data strobe signal to the host device,wherein the eMMC device includes a dedicated data strobe pin, andwherein the host device does not include a dedicated data strobe pin.21. The method of claim 12, comprising: intermittently triggering thecalibration mode to determine the timing relationship between the datastrobe signal and the internal clock signal and to control a delay valueof a delay circuit using the determined timing relationship.